Frequency divider circuits are used, for example, in phase-locked loops of modem communications systems. Phase-locked loops are used to generate a stable signal with a precise frequency. One of the components of a phase-locked loop is a frequency divider circuit, which steps down the frequency of the clock signal generated by the high-frequency oscillator of the phase-locked loop. The stepped-down signal is sent to a phase comparator of the phase-locked loop; the comparator then compares the stepped-down signal with a reference signal and generates an adjusting signal for the oscillator. The phase-locked loop continues to adjust the output frequency of the oscillator until the frequency-divided signal from the frequency divider circuit and the reference signal have the same frequency.
So that a phase-locked loop of this type can generate stable signals at various frequencies, it is necessary for the division ratio in the frequency divider circuit to be adjustable. The frequency divider can thus be switched between various division values. An appropriate control signal is used to set the division ratio to the desired value. A frequency divider circuit with adjustable division ratio is sometimes called a “multimodulus” divider.
FIG. 6 shows part of a known multimodulus divider. The divider shown here comprises essentially a cascade of switchable divider stages, three of which T1-T3 are illustrated. The individual divider stages are connected in series. Each divider stage is designed as a synchronous divider, which divides an input signal by a factor of 2 or by a factor of 3 as a function of the control signal C0, C1, or C2 at its control input 212. This can be explained most clearly on the basis of the synchronous divider stage T2 as an example.
The synchronous divider stage T2 comprises two flip-flop circuits F1 and F2, the clock inputs of which are connected to the input 13 of the synchronous divider stage T2. The data input D of the first flip-flop F1 is connected to the control input 212. The data output Q of the second flip-flop F2 leads to the output 14 of the synchronous divider T2 and is simultaneously connected to a first input A of a logical NAND gate N1. A second input B of the logical NAND gate N1 is connected to the data output Q of the first flip-flop F1.
A high level of a signal is called “logical 1” in the following, whereas a low level is called “logical 0”. When the control signal at the input 212 is at logical 1, a logical 1 is sent from the data output of the first flip-flop to the input B of the NAND gate N1 each time a rising edge of a clock signal arrives at the input 13. The gate N1 in front of the data input D of the second flip-flop F2 then behaves like an inverter, which returns the output signal at the data output Q of F2 via the gate N1 to the data input D. Because, with each rising edge of a clock signal at the input 13, the data output Q of the second flip-flop inverts its state, a signal of half the frequency is present there. The divider T2 therefore divides the frequency of the clock signal present on the input side by 2.
When the control signal present at the control input 212 is at logical 0 at the time that the overall output 14 is at logical 0, and when, in addition, a rising edge arrives at the clock inputs of the flip-flops F1 and F2, the data output Q of the first flip-flop F1 changes to logical 0 and thus forces a logical 1 at the output of the NAND gate N1. At the same time, the overall signal at the output 14 changes to logical 1. The control signal at the input 12 remains at logical 0 even during the second rising edge, so that the overall output continues to send a clock signal at logical 1. This corresponds to the insertion of an extra pulse with half the cycle duration.
After the second rising edge of the clock signal has arrived at the input 13, the control signal at the input 212 is set back to the original state, and another frequency division of the input-side clock signal by the factor of 2 is carried out in the divider stage T2. The suppression of the switching operation thus brings about a division by the factor of 3. This means that an additional positive half-wave is inserted, whereas the negative half-wave retains its original duration.
The divider stages T1, T2, and T3 shown here are based on this concept of suppressing the switching operation. These dividers are therefore also called ⅔-dividers. The lowest division ratio of a cascade consisting of ⅔-dividers is, when these are dividing only by 2. Sending a control signal designed to suppress precisely one clock cycle of the input clock signal corresponds to a division ratio equal to the minimum division ratio nmin+1. To achieve this, the very first divider of the chain must divide by 3 exactly once per complete cycle and otherwise by 2. For a division ratio which corresponds to the minimum division ratio plus 2, the first divider operates with a constant division ratio of 2, whereas the second divider of the chain suppresses one switching operation per complete cycle and thus divides by the factor of 3. For the next division ratio of the overall cascade, the first two divider stages must each divide once per complete cycle by the factor of 3. This binary-weighted scheme can be continued to generate all of the division ratios from the series-connected dividers, ranging from the minimum ratio nmin, when all are dividing only by 2, to the ratio 2*nmin−1.
In the partial view of prior art FIG. 6, the individual control signals for the dividers T1, T2, and T3 are supplied by the control signals C0, C1, and C2, each of which is sent to a logical NAND gate 21 or 21A. This ensures that the corresponding control signal C0, C1, or C2 is always present at the data input D of the first flip-flop F1 of each divider circuit at the beginning of a complete cycle of the divided clock signal available at the output.
For this purpose, a feedback branch is provided. For each divider stage T1-T3, the feedback branch comprises an inverter 22, which is connected to the associated output 14 of the divider stage T1-T3. The outputs of the inverters 22 of the divider circuits T1 and T2, neither of which is the last divider circuit of the overall chain, are each connected to an input B of a logical NAND gate U1, U2. The output of the inverter 22A in the feedback path, this inverter being assigned to the last divider stage T3, is connected both to the input A of the logical NAND gate 21 A and to the input A of the logical NAND gate U2 of the feedback path, this gate being assigned to the divider T2.
The NAND gates 21 and 21A in front of the control inputs 212 of the divider stages T1-T3 are never released by the signals at the input A until all of the following divider stages have a logical 0 at their output. A low logical level of the output signals of all the divider stages T1, T2, T3 in the divider chain, however, means the end of a complete cycle. As a result, a logical 1 is now present at the inputs A, and the control input 212 of the divider stage T1, T2, T3 in question is released. When a rising edge then arrives at the clock input of each divider stage, the corresponding control signal C0, C1, or C2 is sent to the data input of the first flip-flop of the divider stage. Depending on the control signal, the frequency is divided by a factor of 2 or 3. As soon as the signal at the overall output of the divider stage T1 has a value of logical 1, the fact that the NAND 21 is now in the blocking state means that the feedback generates a logical 1 again at the control input 212 of the corresponding divider stage.
The travel time of the feedback signal through the individual logical gates U, however, can be problematic. To guarantee error-free operation when the division ratio is selected, the feedback signal generated by the AND gates U1 and U2 must have released the NAND gate 21, 21A of each divider stage by the time a rising edge of the clock signal CLK arrives at the input of the first divider stage T1. This determines the maximum input frequency of the clock signal CLK on the input side. Delays in the feedback path should therefore be avoided.
For systems with high and very high-frequency input CLK signals, furthermore, the first divider stages should be based on the push-pull technique. The concept of the push-pull technique refers here to difference-signal processing. A push-pull signal is the difference between two signals. The advantages of processing push-pull signals are the greater insensitivity to interference signals and the simplicity of implementation.
In the known exemplary embodiment according to FIG. 6, the divider stage T1 is designed for push-pull signal processing. It is also possible to speak here of a “push-pull divider” T1. For the processing of signals with lower frequencies, divider stages based on the single-ended technique are typically employed. Single-ended dividers are usually designed on the basis of CMOS logic and are slower but, in contrast to the push-pull dividers, they have no static power consumption. In the exemplary embodiment of prior art FIG. 6, the divider stages T2 and T3 are designed as single-ended divider stages. Two converter stages 24 and 25 are required for this heterogeneous structure of a multimodulus divider. The converter stage 24 is connected between the output of the divider T1 and the input of the divider T2 and converts the push-pull signal sent from the push-pull divider stage T1 to a single-ended signal. For the feedback path, a corresponding converter stage 25 is provided, which converts the fed-back single-ended signal to a corresponding push-pull signal.
The conversions performed by the converters, especially by the converter 25, however, cause delays, which in particular reduce the maximum frequency of the input signal. In the known designs, therefore, the single-ended dividers T2 and T3, which are advantageous because of their low power consumption, can be used only in the rear area of a divider cascade, where low frequencies are already present and thus there is sufficient time available for the conversion.